OrthogonalLayout

Layout Style

This layout algorithm arranges the nodes of a given graph such that each edge is drawn as an alternating sequence of horizontal and vertical segments.

It produces compact drawings with no overlapping nodes, few crossings and few bends and is well suited for small and medium-sized sparse graphs.

Orthogonal drawings are common in engineering applications since they are able to provide clear representations of complex networks that can also be optimal with respect to diverse objective functions such as bend minimization or area minimization. Application domains of orthogonal drawings include software engineering, database schema representation, system management, knowledge representation, VLSI circuits and floor planning applications.

Orthogonal layout with default settings

This algorithm also optionally supports directed edge drawings (although not in combination with hierarchically nested graphs or the non-default layoutMode). Application domains of directed orthogonal drawings include, for example, software engineering, database schema and system management.

Sample output of OrthogonalLayout with default settings. Marked edges are considered directed and the layout orientation is top-to-bottom.

Sample output of OrthogonalLayout with edge grouping. All edges are considered directed and the layout orientation is left-to-right.

Also, this algorithm supports hierarchically nested graphs (although not in combination with the directed edge drawings, the from sketch option, or the non-default layoutMode):

Orthogonal layout of a grouped graph with default settings Orthogonal layout of a graph with nested groups

Concept

The orthogonal layout algorithm is based on the topology-shape-metrics approach and runs in three phases:

• Planarization – A planar embedding is computed.
• Orthogonalization – The bends and the angles are computed.
• Compaction – The coordinates for the nodes and edges are determined.

Features

There exist several different main layout modes that the orthogonal layout algorithm supports depending on whether the edges should be routed completely orthogonally, or whether the original size of the nodes should be maintained. The modes are STRICT, FORCED_STRAIGHT_LINE, RELAXED, and can be specified via property layoutMode.

OrthogonalLayout is able to consider edge label data when arranging a graph. This means that the layout algorithm will determine the positions of the nodes and edges such that the edge labels do not overlap with the rest of the layout. Integrated edge labeling can be activated with the edgeLabelPlacement property.

OrthogonalLayoutEdgeDescriptor instances can be used for specifying individual information (e.g. distances) for each edge in the graph. The descriptors are bound to the graph via the layout data property edgeDescriptors. If there is no descriptor assigned to some edges, a default descriptor will be used. To set default descriptors, use defaultEdgeDescriptor.

OrthogonalLayout tries to optimize diverse objective functions such as bend minimization, number of edge crossings, edge length minimization or face maximization. Depending on the qualityTimeRatio and the specified time limit, all or only some of the optimization steps are executed.

For input graphs without group nodes, this layout algorithm is able to detect some specific substructures. If desired, it can handle and arrange them explicitly, making the structure easy to recognize. Supported substructures are trees, chains and cycles. See the corresponding style properties for details: treeSubstructureStyle, chainSubstructureStyle and cycleSubstructureStyle. For the detection of substructures, it is optionally possible to consider nodeTypes, such that only nodes of the same user-defined type can form a substructure.

This layout algorithm handles port placement constraints by applying the PortPlacementStage as a postprocessing step.

Layout Stages

This class provides a configurable pipeline that contains various ILayoutStages. Each ILayoutStage can incorporate preprocessing or postprocessing steps into the layout calculation to streamline the input graph and enhance the resulting layout. Additionally, custom ILayoutStages can be added and executed either before or after the predefined ones.

The following default ILayoutStages are included:

• PortPlacementStage: Assigns edges to ports. The property routeCorrectionPolicy is set to LOCAL_ORTHOGONAL.
• GroupHidingStage: Removes group nodes and their adjacent edges before layout processing, and reinserts them afterward. The property hidingEmptyGroupNodes is set to false and resetEdgePaths is set to true. Note: This stage is disabled by default.
• SubgraphLayoutStage: Filters a graph to include only specific nodes and edges from a subgraph while maintaining the positions of excluded elements. Note: This stage is disabled by default.
• ComponentLayout: Arranges graph components with customizable styles.
• GenericLabeling: Efficiently places node and edge labels. The property fillEmptyScope is set to false and stopDuration is set to ZERO.
• OrientationStage: Changes the layout orientation in four possible directions, with or without mirroring on the x or y-axis. The property edgeLabelPlacement is set to IGNORE.
• SelfLoopRouter: Routes self-loops in a graph, allowing for either orthogonal or rounded routing styles. Note: This stage is disabled by default.
• ParallelEdgeRouter: Routes multiple edges between the same nodes in parallel. Note: This stage is disabled by default.

With these layoutStages the layout algorithm is configured well, so they usually don't need to be changed.